All electronic systems include communication channels for transmitting signals from one component to another. Many electronic systems use clock signals to time the transmission of such signals. In such systems it is important that the duty cycle of clock signal be maintained at a desired ratio. For example, in most computer systems it is important that the clock signal is maintained at a specified duty cycle.
Computer systems generally include a memory subsystem that contains memory devices where instructions and data are held for use by a processor of the computer system. Because the processor is typically capable of operating at a higher rate than the memory subsystem, the operational speed of the memory subsystem has a significant impact on the performance of the computer system.
In the past, the memory devices making up the memory subsystem, such as Dynamic Random Access Memory (“DRAM”), were typically asynchronous devices, i.e., the memory devices stored or output data in response to control signals from a processor. However, asynchronous operation results in a delay between the time that a control signal, e.g., a read command and address value, is received by the memory device and the time that the device responds, e.g., the data becomes available at the output of the memory device. An approach that has been developed to improve memory performance is called double data-rate (“DDR”) and is used in DDR DRAM memory devices. In a DDR DRAM, data during a burst is output on both the rising and falling edges of the clock cycles, which effectively doubles the rate of operational frequency of the memory subsystem.
A DDR memory controller typically contains a clock generation circuit that is configured to generate a clock signal. Frequently, the clock generation circuit is a high-speed, low-jitter clock source that generates a high-speed clock signal CLK0. The clock generation circuit may be an “on-chip” clock generation source or an “off-chip” clock generation source. If an “on-chip” clock generation circuit is used, the circuit may employ a phase-locked loop (“PLL”) with an “off-chip” signal used as a reference. In such an embodiment, the PLL may multiply the clock frequency of the reference signal to obtain a desired high-frequency clock signal.
The clock generation circuit may derive a lower frequency clock signal by using a divider that divides the high-speed clock signal to generate a lower-frequency clock signal that is then output to the DDR memory device. The divider may divide the frequency of the high-speed clock signal by an integer N.
Because data is transferred on both edges of the clock signal in a DDR system, it is desirable, and in some cases necessary, to have a 50% duty cycle. Because of the very high rate of switching associated with the data transfers, the tolerance on duty cycle errors is quite small. Even small errors in a clock's duty cycle can impose a significant reduction on system performance.
Typical duty cycle correction circuits may utilize a field effect transistor (“FET”) based charge pump to generate a voltage that is provided to a shaping circuit via an analog feedback circuit, which is then used to modify the duty cycle. When the desired duty cycle is achieved, the feedback voltage generated from the charge pump stabilizes and remains constant at a value that provides the required correction via the analog feedback circuit. One disadvantage of such a system is that the voltage difference in the charge pump nodes induces an error within the charge pump. Specifically, current characteristics of transistor devices used within the charge pump may vary slightly as the voltages vary. For example, varying drain-to-source voltages can have an effect on the FET channel length, referred to as channel length modulation, which in turn effects the drain-to-source current. Thus, in a charge pump device relied upon to detect small variations in duty cycle based on small changes in FET currents, any voltage variations that may induce channel length modulation in the charge pump FETs may cause the circuit to indicate a locked condition when in fact a small duty cycle offset is present.
Thus, there is a need to more precisely control clock signal duty cycles.